Alibaba's semiconductor division, T-Head, announced day-zero native inference support for its latest open-weight model, Qwen 3.8 27B, running directly on the XuanTie C950 RISC-V server processor. Operating without discrete graphics processing units, the 64-core RISC-V chip delivered sustained decode throughput of 30 tokens per second alongside a time-to-first-token latency of 1.9 seconds.
The benchmark demonstrates how architectural extensions on general-purpose open instruction sets can handle dense foundation models that typically require dedicated accelerator hardware.
Processor Architecture and On-Chip Acceleration
The XuanTie C950 is a 64-bit server processor built around the RISC-V RVA23 profile, featuring 64 out-of-order compute cores clocked up to 3.20 GHz. The processor groups cores into eight-core clusters interconnected by a high-bandwidth AMBA CHI coherent fabric.
Rather than delegating matrix operations to external PCIe-attached GPUs or neural processing units, the C950 integrates matrix and vector calculation pipelines directly into each core cluster:
- Vector Extensions: Native implementation of the standard RISC-V Vector (RVV) instruction set extension for dense mathematical throughput.
- Matrix Acceleration Engines: Dedicated hardware functional units optimized for low-precision matrix multiply-accumulate operations found in transformer attention layers and multi-layer perceptron projections.
- Hierarchical Caching: Dedicated L1 instruction and data caches, configurable per-cluster L2 caches, and a shared L3 cache designed to eliminate inter-core communication bottlenecks during large parameter transfers.
- Hardware Prefetching: Integrated predictive prefetch engines that stream weight matrices and KV cache buffers into execution units ahead of decode requests.
Inference Metrics on Qwen 3.8 27B
Alibaba released Qwen 3.8 27B as an open-weight dense multimodal language model capable of high-tier reasoning and coding workloads while operating within a compact 32GB memory footprint.
When executing the 27-billion-parameter network directly on the XuanTie C950:
- Generation Speed: The processor achieved a steady-state decode throughput of 30 tokens per second.
- Prefill Latency: Time-to-first-token clocked in at 1.9 seconds under standard prompt contexts.
- Hardware Footprint: The workload executes fully on the CPU package, bypassing the need for Nvidia or domestic discrete GPU accelerators.
Strategic Vertical Integration
Achieving 30 tokens per second on a standalone CPU platform addresses two distinct operational constraints for cloud operators and enterprise edge deployments.
First, standard server setups frequently experience GPU shortages or high idle power costs when running smaller 20B to 30B class models for agentic tool execution, preprocessing, and document analysis. Delivering interactive token rates on server CPUs enables datacenters to route secondary workloads away from scarce GPU clusters.
Second, the milestone underscores Alibaba's vertical integration strategy across hardware and software. By developing custom silicon in tandem with open-weight foundation models, Alibaba reduces reliance on proprietary instruction sets like ARM and x86 while establishing an independent compute stack built on open RISC-V standards.
