TSMC is reportedly weighing a price increase of up to 20% for CoWoS, TSMC's advanced packaging technology for combining AI chips with high bandwidth memory, according to a TrendForce summary of supply chain sources cited by Taiwan's Commercial Times. The report lands six days after Nvidia used GTC Berlin to announce capacity deals with six suppliers in substrates, packaging, testing and optical engines.
Both stories are about the steps after a chip is made: packaging, substrates and test.
What the CoWoS report says
CoWoS (Chip on Wafer on Substrate) is TSMC's 2.5D packaging technology. It integrates multiple chips and high bandwidth memory stacks on an interposer, per TSMC's CoWoS page. On the memory side, a recent report says Samsung will make Nvidia's NVHBM base dies on TSMC's 3nm process. TrendForce says CoWoS supply remains tight as increasingly large AI accelerators strain advanced packaging capacity.
Per TrendForce, citing Commercial Times:
- TSMC is reportedly weighing CoWoS price increases of up to 20%, and some packaging lead times are already stretching.
- Foundries and outsourced assembly and test (OSAT) providers are considering another round of CoWoS price increases of 10% to 20%.
- Demand for advanced packaging is spreading beyond AI GPUs to server CPUs and custom ASICs, which adds to a backlog of unfilled orders.
- Equipment lead times have grown to six to eight months, up from three to six months.
- TSMC, which usually negotiates price cuts or extra features at no extra cost, reportedly placed equipment orders at existing prices this year without seeking discounts or upgrades.
The same summary cites Liberty Times as reporting that TSMC has finalized plans to raise wafer prices by 3% to 6% starting January 2027, depending on the process node, with the steepest increases on advanced nodes such as 2nm and 3nm.
None of these numbers come from TSMC itself. They are press reports based on supply chain sources, and the final terms may differ.
Testing is another bottleneck
The report also points to chip testing. Seoul Economic Daily, citing Nomura Securities, reports that final testing of Nvidia Blackwell takes an estimated four times as long as Hopper, and that Rubin could require seven times as long, according to TrendForce. Commercial Times says the longer test cycles further strain packaging and testing capacity, per the same summary.
What Nvidia announced at GTC Berlin
Nvidia's October 21 announcement covers the same parts of the supply chain. Nvidia said it is working with Amkor, IBIDEN, King Yuan Electronics (KYEC), Samsung Electro-Mechanics, Siliconware Precision Industries (SPIL) and Unimicron. The main points:
- Substrates. Nvidia plans to increase substrate capacity for its products by 2.5x over the next three years. It is giving IBIDEN a multibillion-dollar capacity reservation advance for its Ono Plant in Japan, which targets 3x current capacity, with additional capacity expected to begin ramping in the first quarter of 2028. Samsung Electro-Mechanics joins the substrate supply chain with capacity in South Korea and new factories in Sejong and Busan. A capacity reservation agreement supports Unimicron's KF expansion in Taiwan, which is expected to add capacity from the second quarter of 2027 and reach full capacity by mid-2028.
- Advanced packaging. Nvidia and Amkor target a greater than 300% increase in interposer wafer capacity in South Korea by the end of 2028.
- Testing. Nvidia expects its total semiconductor testing capacity to double from calendar 2026 to 2027. A $1.1 billion capacity reservation advance to KYEC supports new U.S. testing facilities, with high-volume production targeted for April 2027. Expanded testing in Singapore is expected to reach high-volume production in February 2027.
- Co-packaged optics. Nvidia and SPIL target a 15x increase in optical-engine capacity in Taiwan by mid-2027, with aims for another doubling by the end of 2028.
"Demand is extraordinary. Capacity is the constraint," Nvidia CEO Jensen Huang said in the release, also quoted by Tom's Hardware.
Every figure is a planned capacity target, and Nvidia gives no current baseline volumes, as StorageReview notes.
How much CoWoS capacity is coming
TSMC is still expanding. Analysts cited by Commercial Times estimate monthly CoWoS capacity will exceed 130,000 wafers in 2026 and target 200,000 in 2027. Goldman Sachs projects TSMC's CoWoS capacity at 1.275 million wafers in 2026, then 2.73 million in 2027 (up 114%) and 3.48 million in 2028 (up another 27%), per TrendForce.
TSMC chairman and CEO C.C. Wei said at the latest earnings call that its 5x reticle-size packaging is already in mass production with strong yields, and confirmed development of 9x and 14x versions, the same summary reports. TSMC is also advancing CoPoS to support larger packages at lower costs, and Commercial Times points to a 2028 timeline for 14x packaging, per TrendForce.
Why it matters
TrendForce says demand for advanced packaging now comes from server CPUs and custom ASICs as well as AI GPUs, and it links the pricing pressure to that wider demand. None of the reports say how much of a CoWoS price increase would pass on to chip prices.
Nvidia's deals show the other side of the same problem. Tom's Hardware says the deals, with roadmaps that stretch through 2028, secure capacity for Nvidia. For example, by 2028, production allocated to Nvidia is projected to account for a significant portion of Samsung Electro-Mechanics' total annual package substrate production capacity, per Nvidia's release.
Most of the dated targets in Nvidia's release fall in 2027 and 2028.
