IBM unveiled the industry's first dual-architecture mainframe processor at the annual Hot Chips conference, detailing custom silicon capable of natively executing both IBM Z (s390x) and Arm (Arm64) instruction set architectures on the exact same physical cores.
Fabricated on a leading-edge 2-nanometer process node, the upcoming processor is engineered to bridge traditional enterprise transaction processing with the modern, Arm-dominated software ecosystem, particularly containerized AI frameworks and large language model inference pipelines.
Bilingual Core Microarchitecture and KVM Virtualization
Rather than integrating separate, dedicated Arm coprocessor cores onto the die periphery, IBM designed all 11 high-performance cores on the chip to dynamically switch instruction sets at nanosecond latency.
- Process Node and Clock Speed: The processor features 11 cores built on a 2nm node, operating at base frequencies exceeding 5.7 GHz.
- Dynamic Instruction Switching: Using the open-source KVM hypervisor, cores switch between Arm64 Linux and Linux on Z virtual machines as tasks are dispatched. Because the execution mode switch occurs in nanoseconds while virtual machine slices run for milliseconds, switching overhead amortizes near zero.
- Enterprise Isolation: Mission-critical z/OS transaction environments run in isolated logical partitions on the same die, allowing core financial ledgers and modern Arm software stacks to share cache hierarchies and memory fabrics.
- Binary Compatibility: The chip provides 100% binary compatibility for standard Arm Linux distributions, such as Red Hat Enterprise Linux for Arm, without requiring software emulation or recompilation.
On-Chip AI Inference and Next-Generation Spyre Accelerators
The processor continues IBM's dual-tier AI compute strategy, coupling low-latency on-chip inference with high-throughput external acceleration:
- In-Transaction Inference: An integrated on-chip neural accelerator enables real-time scoring (such as fraud detection) inside high-volume payment transaction loops.
- Dedicated I/O Processing: An integrated Data Processing Unit (DPU) offloads storage and networking traffic.
- Next-Generation Spyre LLM Accelerator: IBM also previewed an updated Spyre accelerator card equipped with High Bandwidth Memory (HBM). The dedicated card is designed to execute larger foundation models and agentic workflows, covering autonomous IT operations, unstructured document extraction, and insurance claims processing.
Strategic Shift Toward the Arm AI Ecosystem
The architecture represents the first major hardware deliverable from the partnership IBM and Arm announced in April. By Arm's estimates, nearly half of compute capacity delivered to cloud hyperscalers in 2025 utilized Arm architecture, accompanied by a developer base exceeding 22 million engineers.
Historically, bringing cloud-native tooling, observability agents, and machine learning runtimes (such as PyTorch and ONNX) to the mainframe required labor-intensive manual ports to s390x. Enabling native Arm64 execution on mainframe silicon allows enterprises in regulated sectors to deploy modern open-source AI tooling directly where their primary system of record resides.
IBM indicated the dual-architecture processor will debut in the hardware generation succeeding the current z17 system, placing expected availability around 2028.
