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  • OpenAI Unveils Jalapeño Custom Inference Chip Benchmarks at Hot Chips 37

    OpenAI presented the first architecture and benchmark disclosures for its custom inference chip, code-named Jalapeño, during the 37th Hot Chips conference. In published test data and technical disclosures, OpenAI reported that Jalapeño achieves 1.5x to 1.9x higher performance per watt and 1.7x to 3.6x lower end-to-end latency compared to Nvidia Blackwell GB200 and GB300 systems on production LLM workloads. Developed in co-design partnership with Broadcom, Jalapeño represents OpenAI's initial ha

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  • Intel Details 256-Core Xeon 7 and 480GB Crescent Island Inference GPU at Hot Chips 2026

    At the Hot Chips 2026 conference, Intel outlined architectural disclosures for three upcoming computing platforms tailored for AI workflows: the Xeon 7 enterprise processor (codename Diamond Rapids), the Crescent Island data center inference GPU, and the Wildcat Lake client processor (Intel Core Series 3). The announcements detail Intel's shift toward modular multi-die packaging, open chiplet interconnect standards, and expanded on-chip memory to meet the computational demands of multi-agent AI

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  • OpenAI Publishes Benchmark Results for Jalapeño Custom Inference Silicon

    OpenAI Publishes Benchmark Results for Jalapeño Custom Inference Silicon OpenAI has shared its first empirical performance data for Jalapeño, the custom inference processor co-developed with Broadcom. Presented at the Hot Chips conference and published in an engineering report, the benchmark results evaluate the 700-watt accelerator across open-weight frontier models against Nvidia GB200 and GB300 systems using SemiAnalysis's InferenceX test suite. The published metrics focus on serving effici

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  • Apple Debuts M6 on 2nm and Quad-Die M5 Ultra with 512GB Memory for Local LLMs

    Apple has introduced two new silicon architectures aimed at local artificial intelligence workloads: the M6, manufactured on a 2-nanometer process, and the M5 Ultra, a quad-die processor offering up to 512GB of unified memory. The chips debut across updated desktop lines. The M6 powers an entry Mac mini starting at $899, while the M5 Ultra configures into the Mac Studio, where M5 Max base configurations start at $2,499. Both product lines are scheduled to begin customer deliveries on September

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  • Xiaomi Unveils Custom Silicon Roadmap with 6nm Xring O100 AI Accelerator and 3nm D100 Smart-Driving Processor

    Xiaomi has unveiled details of its custom semiconductor roadmap, introducing two specialized AI processors alongside its next-generation mobile system-on-chip: the 6-nanometer Xring O100 near-memory AI accelerator and the 3-nanometer Xring D100 autonomous driving chip. Both processors are manufactured by TSMC and have completed hardware validation ahead of planned commercial rollouts. The announcements follow a reported investment of more than 21 billion yuan ($3.1 billion) by Xiaomi into in-ho

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  • Marvell Issues Google 2.2B Stock Warrant in Custom AI Silicon Deal

    Marvell Technology has granted Alphabet's Google a warrant to purchase up to 58.9 million shares of common stock at an exercise price of $206.58 per share, establishing an equity arrangement valued at up to $12.18 billion. The agreement expands the companies' partnership to co-develop custom artificial intelligence silicon, specialized networking, and next-generation datacenter infrastructure. Following the announcement, Marvell shares rose more than 11% in premarket trading, while primary cust

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  • Velaura AI Raises 10M Series A at B Valuation for Low-Power AI Silicon

    Velaura AI Raises $110M Series A at $1B Valuation for Low-Power AI Silicon Velaura AI has closed a $110 million Series A funding round at a valuation exceeding $1 billion. The financing was led by Seligman Ventures, with participation from Capricorn Investment Group alongside existing backers including Samsung Catalyst Fund, StepStone Group, Maverick Silicon, Celesta Capital, and Mayfield. The capital will fund the commercialization and deployment of Velaura's silicon IP and physical design te

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