Cerebras Unveils CS-4 Rack-Scale System Powered by Three WSE-3 Turbo Chips and Nexus Architecture
Cerebras Systems has announced the CS-4, a rack-scale AI accelerator system designed around three of its next-generation Wafer Scale Engine 3 Turbo (WSE-3 Turbo) chips and a modular hardware architecture dubbed Nexus. Cerebras confirmed that initial customer shipments for the CS-4 are scheduled to begin in the current quarter.
The new system marks a structural shift from Cerebras's single-wafer CS-2 and CS-3 enclosures toward a disaggregated rack architecture. By packing three full-wafer processors into a single unified rack enclosure, the CS-4 is engineered to deliver up to 30 times faster token generation speeds on large language model inference compared to conventional GPU clusters, alongside a 10-fold improvement in throughput per watt relative to the previous-generation CS-3.
Wafer-Scale Backpacks and Millimeter Power Delivery
The foundation of the CS-4 design is the modular Nexus platform, which separates data center facility infrastructure (power, cooling, and network distribution) from the core compute layer. Cerebras packages each WSE-3 Turbo wafer into an autonomous "Wafer-Scale Backpack" assembly. Each backpack integrates the wafer processor, high-density power conversion hardware, direct liquid cooling distribution, and high-speed I/O into a consolidated 3D module with 50 percent fewer discrete components than previous server designs.
A central engineering priority in the CS-4 is power delivery density. Cerebras positioned power conversion circuitry 0.5 millimeters from the wafer processor silicon, compared to the roughly 50-millimeter distance typical on traditional server boards. This reduction in trace length minimizes board-level resistive losses and enables delivery of up to twice the electrical power to the wafer, driving higher operational clock frequencies during sustained inference workloads.
Under the Nexus deployment model, data centers can install and validate the passive "PowerRack" shell (connecting facilities power, chilled fluid loops, and optical networking) prior to receiving compute units. Compute backpacks then slide directly into the pre-tested rack bays, reducing installation and commissioning timelines from days to several hours.
Direct Switchless Interconnect and Low-Latency Scaling
To coordinate multiple wafer processors without introducing external network bottlenecks, the CS-4 introduces a programmable wafer I/O subsystem that doubles total interface bandwidth and cuts communication latency.
The I/O architecture allows wafers within the same rack, or across adjacent racks, to establish direct point-to-point links without routing traffic through intermediary InfiniBand or Ethernet network switches. Cerebras states that this direct link structure achieves wafer-to-wafer interconnect latencies as low as 2 microseconds.
This low latency is designed to sustain interactive decoding speeds on multi-trillion-parameter frontier models. While conventional GPU clusters face severe communication overheads during tensor and pipeline parallel operations across thousands of discrete chips, Cerebras claims the CS-4 can maintain generation rates exceeding 1,000 tokens per second on models scaled past 10 trillion parameters.
First shipments of the CS-4 system commence this quarter as hyperscalers and frontier research labs evaluate wafer-scale alternatives to scale-out GPU infrastructure.
